1. Field of the Invention
The present invention relates to a pulse generator, and more particularly, to a pulse generator which can variably control a pulse length.
2. Description of the Prior Art
FIG. 1 is a circuit diagram of a conventional pulse generator.
In FIG. 1, the conventional pulse generator consists of a delay element(66), inverters(67, 69, 71), and NAND gates(68, 70, 72).
The delay element 66 is reset in response to a reset signal RESET.sub.--, and outputs a delay a signal DWL. The inverter 67 inverts an output signal of the delay element 66 and outputs a signal TOR.sub.--. The inverter 69 inverts and outputs a write enable signal WE. The inverter 71 delays an output signal of the delay element 66 and outputs a signal TOW.sub.--. NAND gate 68 performs a NAND-operation of the signal TOR.sub.--, a signal DWL, and an output signal of the inverter 69, and outputs a NAND-operated signal. A NAND gate 70 performs a NAND operation of the write enable signal WE, a signal TO, and the signal TOW.sub.--, and outputs its NAND-operated signal. NAND gate 72 performs a NAND operation of the output signals of NAND gates 68, 70, and a signal SETPLS and outputs an output signal PULSE.
FIG. 2 is a detailed circuit diagram of the delay element shown in FIG. 1.
In FIG. 2, the delay element 66 consists of a NAND gate 80, an inverter 81, and a capacitor 82.
A NAND gate 80 performs a NAND operation of two inputs signals and outputs a NAND-operated signal. A capacitor 82 is connected between an output terminal of NAND gate 80 and a ground. An inverter 81 inverts an output signal of NAND gate 80 and outputs the inverted signal.
FIG. 3A-G is an operational timing diagram for explaining an operation of the conventional pulse generator.
With reference to FIG. 3A-G, the operation of the pulse generator shown in FIG. 1 will be described below.
The operation of the pulse generator will be explained in reference to a read mode and a write mode. The read mode and write mode is controlled by the write enable signal WE, and the pulse generator is operated during the write mode when the write enable signal WE is a "high" level, whereas, during the read mode when the write enable signal is a "low" level.
When the write enable signal WE is "low" level of the read mode, and if a reset signal RESET.sub.-- transits from the "low" level to the "high" level as shown in FIG. 3A, the delay element 66 can be operated. At this time, if the signal TO of a "high" level is inputted as shown in FIG. 3B, the inverter 67 inverts the signal delayed by the delay element 66 and outputs a signal TOR.sub.-- of a "low" level as shown in FIG. 3E. The inverter 71 inverts the signal delayed by the delay element 66 and outputs the signal TOW.sub.-- of a "low" level as shown in FIG. 3F. The NAND gate 70 performs a NAND operation of the signal TO of "high" level, the write enable signal WE of "low" level, and the signal TOW.sub.-- of a "low" level, and outputs a signal of "high" level. The NAND gate 68 outputs a signal of a "high" level since the write enable signal WE is "low" level. Accordingly, NAND gate 72 outputs an output signal PULSE of a "high" level as shown in FIG. 3G, regardless of state of a signal SETPLS. The NAND gate 70 performs a NAND operation of the signal TO, the Write enable signal WE, and the signal TOW.sub.-- of a "low" level, and outputs a signal of a "high" level. The NAND gate 72 performs a NAND operation of the output signals of the NAND gates 68, 70, and the signal SETPLS of a "high" level, and makes the output signal PULSE to be a "low" level. By performing the above operation, the pulse generator can generate a pulse having a short pulse length in the read mode.
When the write enable signal WE is a "high" level of the write mode, and the reset signal RESET.sub.-- transits from a "low" level to a "high" level as shown in FIG. 3A, the delay element 66 delays the signal DWL for a predetermined time period and outputs the delayed signal. The inverter 71 inverts the signal delayed by the delayed element 66 and outputs a signal TOW.sub.-- as shown in FIG. 3F. The NAND gate 70 performs a NAND operation of the signal TO, the write enable signal, and the signal TOW.sub.-- of a "high" level and outputs a signal of a "low" level. The NAND gate 68 outputs a signal of a "high" level during the output signal of the inverter 69 maintains a "low" level. The NAND gate 72 performs a NAND operation of the output signal of NAND gate 68 of a "high" level and the output signal of the NAND gate 70 of a "low" level, and a signal SETPLS, and outputs the output signal PULSE of a "high" level as shown in FIG. 3G. By performing the above operation, the pulse generator can generate a pulse having a long pulse length in the write mode.
The circuit shown in FIGS. 1 and 2 is disclosed in U.S. Pat. No. 5,258,952. In the above explanation, only the pulse generator is described, but a circuit for generating various pulses RESET.sub.--, DWL, TO, SETPLS which is used as input signals of pulse generator shown in FIG. 1 by using an address state transition pulse ATD and a data transition pulse DTD generated inside of a semiconductor memory device is described in U.S. Pat. No. 5,258,952, which is incorporated herein by reference.
The conventional pulse generator is disadvantageous since the circuit construction is complicated, and there are a large number of the delay element, thereby increasing a chip size.